A C - 2 7 0 0 ( 1 0 / 1 9 9 4 ) WESTERN DIGITAL NO MORE PRODUCED Native| Translation ------+-----+-----+----- Form 3.5"/SLIMLINE Cylinders | 1416| | Capacity form/unform 730/ MB Heads 4| 16| | Seek time / track 11.0/ 4.0 ms Sector/track | 63| | Controller IDE / ATA2 FAST/ENHA Precompensation Cache/Buffer 64 KB ADAPTIVE Landing Zone Data transfer rate 5.260 MB/S int Bytes/Sector 512 13.300 MB/S ext DMA Recording method RLL 1/7 operating | non-operating -------------+-------------- Supply voltage 5/12 V Temperature *C 5 55 | -40 60 Power: sleep 0.5 W Humidity % 8 80 | 5 95 standby 0.5 W Altitude km -0.300 3.000| -0.300 12.000 idle 4.6 W Shock g 10 | 150 seek 8.1 W Rotation RPM 4500 read/write 4.6 W Acoustic dBA 39 spin-up 12.7 W ECC Bit ON THE FLY,REED SOLOMON MTBF h 300000 Warranty Month 36 Lift/Lock/Park YES Certificates CSA,FCC,IEC950,TUV,UL1950 ********************************************************************** L A Y O U T ********************************************************************** WESTERN AC1365/2700/1425/2850 TECHNIC. REFERENCE GUIDE 79-860012-000 +---------------------------------------------------------+ | |XX | |XX J2 | |XX Inter- | |XX face | |XX | |.X | |XX | |XX | |XX | |XX | |X1 | |+-+ | || |J8 | |+-1 | |XX Power | |XX J3 +---------------------------------------------------------+ 1 J2 J8 J3 +39------------------------------------1++5-3-1++-------+ |o o o o o o o o o o o o o o o o o o o o||o o o||O O O O| |o o o o o o o o o o o o o o o o o o o||o o o||4 3 2 1| --+40------------------------------------2++6-4-2+++-+-+-++---- | | | +12V (Pin 20 keyed) | | +- GND | +--- GND +----- +5V ********************************************************************** J U M P E R S ********************************************************************** WESTERN AC1365/2700/1425/2850 TECHNIC. REFERENCE GUIDE 79-860012-000 Jumper setting ============== J8 Master/Slave/Cable Select Configuration ------------------------------------------- +5-3-1+ Single (Neutral Position) |xxx o| Factory default. The jumper in this position has no effect |o o o| on single hard drive configurations. +6-4-2+ +5-3-1+ Single Drive +5-3-1+ Master Drive |o o o| Configuration |X o o| Configuration |o o o| |X o o| (Dual Drives) +6-4-2+ +6-4-2+ +5-3-1+ Slave Drive +5-3-1+ Cable Select |o X o| Configuration |o o X| Configuration |o X o| (Dual Drives) |o o X| (Dual Drives) +6-4-2+ +6-4-2+ The Caviar can be assigned as either a single, master, or slave drive. Caviar drives are shipped with a jumper shunt in the neutral storage position (across pins 5 and 3). Single Drive Mode ----------------- If you are installing the Caviar drive as the only intelligent drive in the system, you do not need install jumpers on the J8 connector. This is considered a standard single drive installation, and no jumpers are required. Note that even with no jumper installed, the Caviar checks the DRIVE ACTIVE/SLAVE PRESENT (DASP) signal to de- termine if a slave intelligent drive is present. If you have a dual installation (two intelligent drives), you must designate one of the drives as the master and the other as the slave drive. The jumper pins on the J8 connector need to be configured for the dual installation. Master Drive Mode ----------------- To designate the drive as the master, place a jumper shunt on pins 5-6. With the Caviar configured as the master drive, the Caviar assumes that a slave drive is present. The jumper on pins 5-6 is optional if the slave drive follows the same protocol (Common Access Method AT Bus Attachment) as the Caviar. Slave Drive Mode ---------------- To designate the drive as the slave, place a jumper shunt on pins 3-4. When the Caviar is configured as the slave drive, the Caviar delays spin up for three seconds after power-up reset. This feature prevents overloading of the power supply during power-up. Cable Select (CSEL) ------------------- Caviar also supports the CSEL signal on the drive cable as a drive address selection. Place a jumper shunt on pins 1-2 to enable this option. When enabled, the drive address is 0 (Master) if CSEL is low, or 1 (Slave) if CSEL is high. Do not install the CSEL jumper shunt when installing the Caviar drive in systems that do not support the CSEL feature. J3 DC Power and pin connector assignments ------------------------------------------- +------------+ pin 1 +12 V | 4 3 2 1 | pin 2 GND +------------+ pin 3 GND pin 4 + 5 V ********************************************************************** I N S T A L L ********************************************************************** WESTERN AC1365/2700/1425/2850 TECHNIC. REFERENCE GUIDE 79-860012-000 Notes of Installation ===================== Installation direction ---------------------- horizontally vertically +-----------------+ +--+ +--+ | | | +-----+ +-----+ | | | | | | | | | +-+-----------------+-+ | | | | | | +---------------------+ | | | | | | | | | | | | | | | | | | +---------------------+ | +-----+ +-----+ | +-+-----------------+-+ +--+ +--+ | | | | +-----------------+ The drive will operate in all axis (6 directions). Orientation ----------- The Caviar can be mounted in the X, Y, or Z axis depending upon the physical design of your system. It is recommended that the drive be mounted with all four screws grounded to the chassis. Determining Your Configuration ------------------------------ You can configure the Caviar in one of two ways: 1. The drive is cabled directly to a 40-pin connector on the mother- board, or 2. The drive is cabled to an adapter card mounted in one of the expansion slots in the computer. Both configurations use a 40-pin host interface cable. If you are using the Caiar drive as one of two hard disk drives in the computer (dual installation), you may use either configuration. In dual installations, you must use a 40-pin host interface cable with three connectors and daisy-chain the two drives to the mother- board or adapter card. Dual Installations ------------------ Dual Installations require a master/slave drive configuration, where one drive is designated as the primary (master) drive and the other is designated as the secondary (slave) drive. The Caviar drive is compatible in dual installations with other intelligent drives that support a master/slave configuration. If your installation requires the use of an adapter card, it is useful to know that you may also be able to connect your floppy drive(s) to the adapter card. Dual Drive Option ----------------- The Caviar supports ATA dual drive operations by means of configura- tion options for master or slave drive designation. The Caviar is 100% ATA compatible regarding the timing PDIAG and DASP signals. The SDH Register contains the master/slave select bit for the Caviar. The DASP signal is a time-multiplexed indicator of "Drive Active or Slave Present" on the Caviar's I/O interface. At reset, this signal is an output from the slave drive and an input to the master drive, showing that the slave drive is present. For all times other than reset, DASP is asserted at the beginning of command processing and released upon completion of the command. If the master drive option has been configured, the Caviar will not respond to commands or drive status on the interface when the slave bit is selected in the SDH Register. Mounting the Drive ------------------ For dual installations, it is usually easier to completely install one intelligent drive in the lower position first. The order of intelligent drives is unimportant if you are using to Western Digital drives. As explained previously, one must be jumpered as the master drive and the other as the slave drive. When installation is complete the drives are daisy-chained together. Cabling and Installation Steps ------------------------------ Make sure your interface cable is no longer than 18 inches (including daisy chaining) to minimize noise that is induced on the data and control buses. The total cable length of an installation cannot exceed 18 inches. When connecting two drives together, use a daisy- chain cable that has three 40-pin connectors. Caution: You may damage the Caviar drive if the interface cable is not connected properly. To prevent incorrect connection, use a cable that has keyed connectors at both the drive and host ends. Pin 20 has been removed from J2 connector. The female connector on the interface cable should have a plug position 20 to prevent incorrect connection. Make sure that pin 1 on the cable is connected to pin 1 on the connectors. Screw Size Limitations ---------------------- The Caviar is mounted to the chassis using 6-32 screws. Recommended screw torque is 5 in-lb. Maximum screw torque is 10-in-lb. CAUTION Screws that are too long will damage circuit board components. The screw must engage no more than six threads (3/16 inch). Side mounted screws should engage a maximum of .188 inches (3/16"). Bottom mounted screws should engage a maximum of .250 inches (1/4"). Power Connectors and Cables --------------------------- Power Connector: 4-pin AMP P/N 84069-1 or equivalent Mating Connector: Body AMP 1-480424-0 or equivalent Pins AMP 60619-4 or equivalent Power Cable Wire Gauge 18 AWG Universal Translation --------------------- The Caviar implements linear address translation. The translation mode and translated drive configuration are selected by using the Set Drive Parameters command to issue head and sector/track counts to the translator. Caviar supports universal translation, therefore, any valid combination of cylinder, head and SPT can be assigned to the drive, as long as the total number of sectors is not greater than the physical limits. The product of the cylinder, head and sectors/track counts must be equal to or less than the maximum number of sectors available to the user. The maximum number of sectors per drive are: AC1365 - 713,664 AC1425 - 833,616 AC2700 - 1,427,328 AC2850 - 1,667,232 Each sector consists of 512 bytes. The minimum values for any translation parameter is one. The maximum value for any translation parameter is as follows: Sectors/Track - 255 Heads - 16 Cylinders/Drive - 2048 The values in the Sector Count Register and the SDH Register determine the Sectors Per Track (SPT) and heads. Regardless of the values of the SPT and the heads, Caviar is always in the translation mode. Grounding --------- It is reommended that the drive be mounted with all four screws in the side grounded to the chasis. Installing the Controller Card ------------------------------ If you are installing an controller card, set the controller card configuration before attaching any cables or installing the card into the slot. NOTE Remove or disable any existing floppy controller which is being replaced by the controller card/floppy controller. ********************************************************************** F E A T U R E S ********************************************************************** WESTERN AC1365/2700/1425/2850 TECHNIC. REFERENCE GUIDE 79-860012-000 General Description ------------------- The Caviar AC1365, AC2700, AC1425 and AC2850 Enhanced IDE drives provide 365, 730, 425 and 850 MBs of formatted storage in a low-profile, 1-inch, 3.5-inch form factor. Western Digital designed these hgh-performance, cost-focused solutions to accommodate the improved processor speeds found in newer systems. The AC1365/AC2700 and AC1425/AC2850 combine the electronic architecture featured in previous Caviar disk drives with a new, cost-optimized mechanical platform. This new mechanism will leverage our current successful design concepts resulting in higher performance, increased rigidity, and lower acoustics, with the added benefit of facilitating easier customer drive qualification. The AC1365, AC2700, AC1425 and AC2850 feature CacheFlow3, Western Digital's third generation advanced caching algorithm. CacheFlow3 increases performance by adapting read and write methodology on-the-fly and works in conjunction with the advanced disk caching capabilities of today's major operating systems. New random write caching improves random write performance up to 30 percent. The AC1365, AC2700, AC1425 and AC2850 support high-speed 11.1 MByte/sec Mode 3 PIO and 13.3 Mbytes/sec Mode 1 multi-word DMA host transfer capabilities. This enables VESA VL or PCI local bus IDE integration. An average read seek time of 10 ms and a spindle latency of 6.67 ms combine to provide fast mechanical access to data that is uncached. The AC1365, AC2700, AC1425 and AC2850 support advanced power management capabilities that can reduce power requirements up to 80 percent. These capabilities are exploited by today's new systens to reduce annual system energy demands which saves both money and the environment. DMA --- DMA Read and DMA Write commands are ATA compatible and supported in systems implementing EISA (type B) and PCI (type F) DMA. DMA data transfers provide significant improvement in CPU bandwidth over conventional PIO data transfers. The system CPU is free to accomplish other tasks while the Caviar drive transfers data directly to/from system memory. Advanced Host Transfer ---------------------- The AC1365, AC2700, AC1425 and AC2850 support Mode 3 PIO (11.1 Mbytes/s) and Mode 1 multi-word DMA (13.3 Mbytes/s) as defined by the Small Form Factor 8011 and ATA-2 standards. To achieve Mode 3 PIO burst transfers, hard disk drives must be able to throttle the host via the IORDY signal. Systems typically require a high-speed VL or PCI local bus in order to support Mode 3 PIO. Logical Block Addressing (LBA) ------------------------------ The AC1365, AC2700, AC1425 and AC2850 support both LBA and CHS based addressing. LBA addressing support is included in advanced operating system device drivers and ensures high-capacity disk integration. It also offers higher performance on file systems that are LBA based, thus avoiding unnecessary LBA to CHS conversion within the operating device system driver. LBA mode is enabled by setting bit 5 in the SDH task file register. When entering a logical block address, the task file registers are as follows: Task File Register | LBA Bits -------------------+------------ Sector Number | 7-0 -------------------+------------ Cylinder Low | 15-8 -------------------+------------ Cylinder High | 23-16 -------------------+------------ SDH (Bits 3-0) | 27-24 When the LBA bit is set, logical block addressing is recognized by the following commands: Read Sector Recalibrate Write Sector Seek Read Verify Format Track Read DMA Read Multiple Write DMA Write Multiple For all other commands, the LBA bit is ignored. Sectors on the drive have a 1:1 corresponding logical block address, with the first data sector on the drive being LBA 0. The task file following a command sent with the LBA bit set contains LBA parameters. The AC1365, AC2700, AC1425 and AC2850 support both LBA and CHS-based addressing. Support for LBA addressing is included in advanced operating system device drivers and ensures high-capacity disk integration. It also offers higher performance on file systems that are LBA-based, thus avoiding unnecessary LBA to CHS conversion within the operating device system driver. Zoned Recording --------------- The AC1365, AC2700, AC1425 and AC2850 drives employ Zoned Recording to increase the data density on the outer tracks of the drive. The outermost tracks contain more sectors than the innermost tracks, thereby increasing the total capacity of the drive. Advanced Defect Management -------------------------- The Caviar is preformatted (low-level) at the factory and comes with a full complement of defect management functions. Extensively tested during the manufacturing process, media defects found during intelligent burn in are mapped out with Western Digital's high performance defect management technique. No modifications are required before installation. Reed Solomon ECC On-the-Fly --------------------------- The Caviar implements Reed Solomon error correction techniques to obtain extremely low read error rates. This error correction algorithm corrects errors on-the-fly without any performance penal- ties. It allows for hardware corrections of up to a 24-bit error span on-the-fly. Automatic Defect Retirement --------------------------- If the Caviar drive detects a defective sector while writing, it automatically relocates the sector without end-user intervention. Embedded Servo Control ---------------------- The Caviar festures an embedded servo concept as the means of providing sampled position feedback information to the head position servo system. Servo bursts are located along a radial path from the disk position servo system. This high sampling rate supports the high frequency servo bandwidth required for fast access times as well as highly accurate head positioning. The embedded servo concept provides the means of generating accurate feedback information without requiring a full data surface as would a dedicated servo control concept. Seek Time --------- Average Seek - Read 10 Milliseconds - Write 12.5 Milliseconds Track-to-Track Seek 4 Milliseconds Maximum Seek 23 Milliseconds Index Pulse Period 13.33 Milliseconds Average Latency 6.67 Milliseconds Defect Management ----------------- Every Caviar undergoes factory-level intelligent burn in, which thoroughly tests for and maps out defective sectors on the media before the drive leaves the manufacturing facility. Following the factory tests, a primary defect list is created. The list contains the sector cylinder and head numbers for all defects. Defects managed at the factory are sector slipped. Grown defects that can occur in the field are handled by realocation to spare sectors on the inner cylinders of the drive. Format Characteristics ---------------------- The Caviar is shipped from the factory preformatted (low level) with all the known defects mapped out. In order to be compatible with existing industry standard defect management utility programs, the Caviar supports logical format command. When the host issues the Format Track command, the Caviar performs a logical version of this command in response to the host's interleave table request for good and bad sector marking or assign/ unassign the sector to/from an alternate sector. If the host issues the Format Track Command during normal operating modes, the data fields of the specified track are filled with a data pattern of all zeros. The Format Track Command can be used to mark/ unmark bad sectors, and reassign unrelocated sectors. Drive Electronics ----------------- Caviar's intelligence resides in the specialized electronic components mounted on the four-layer printed circuit board assembly. The Caviar consists of the following drive electronic components: - WD61C25 Winchester Disk Controller - Buffer RAM - WD61C12 Servo Controller - WD10C28 Data Separator/Frequency Synthesizer/ENDEC - Microcontroller - Pulse Detector - Spindle Motor Driver - Actuator Driver WD61C25 Winchester Disk Controller ---------------------------------- The WD61C25 integrates a high-performance, low-cost Winchester formatter/controller, CRC/ECC generator/checker, host interface and buffer manager into a single, 100-pin MQFP device. The CRC/ECC generator/checker calculates ECC for the data field. The host inter- face directly connects to the host system bus via internal 24 mA drivers. The buffer manager controls the buffer RAM and handles the arbitration between the host interface and drive controller. Buffer RAM ---------- A 64-Kbyte static RAM buffer enhances data throughput by buffering sector data between the Caviar and the AT system bus. The buffer is accessed by two channels, each having a separate 16-bit address and byte-count register. The channels operate simultaneously, accepting read and write operations from two data paths. WD61C12 Servo Controller ------------------------ The WD61C12 provides servo discrimination, track address capture and measures servo burst amplitudes. A servo burst is a momentary servo pattern used in embedded servo control implementations that is positioned at regular intervals on each track. The WD61C12 also provides spindle motor control. WD10C28 Data Separator/Frequency Synthesizer/ENDEC -------------------------------------------------- The WD10C28 handles the sensitive read/write signals between the WD61C25 and the read channel circuitry. (Read channel data refers to previously written data with phase, frequency and write splice noise.) It also removes the noise, sends clean digital read signals to the WD61C25, conditions write data to be recorded on the drive, and precisely clocks and encodes/decodes data to and from the WD61C36. The WD10C28 has a built-in frequency synthesizer to set the proper frequency for each zone. Write Precompensation Register ------------------------------ The Write Precompensation Register is ignored during normal write operations since the Caviar automatically determines the proper write precompensation. The contents of this register are used by the following commands. - Set Features - Rest - Read Drive State - Restore Drive State - Mode Sense - Mode Select Execute Diagnostics (90H) ------------------------- The Execute Diagnostics command causes the Caviar to execute its self-diagnostics and to report a result code in the Error Register as follows: 01 = No Error 02 = Not Applicable 03 = Buffer RAM Error 04 = WD61C25 Register Error 05 = Microcontroller Internal RAM Error or ROM Checksum Error 8x = Slave Drive Failed. Error Reporting --------------- The following table lists all the valid error conditions which can occur for a given command. The Caviar drive checks the Command Register at the start of a command to determine if any condition exists which could result in a terminated command. The command is then attempted. Any subsequent error terminates the command at the point where it is encountered. +----------------------+------------------------------------------+ |Command | Error Message | +----------------------+---+---+----+--+----+---+---+----+---+----+ | |BBD|UNC|IDNF|AC|DRDY|DWF|DSC|CORR|ERR|HOST| | | | | | | | | | | |FIFO| +----------------------+---+---+----+--+----+---+---+----+---+----+ |Recalibrate (1) | | | |V | V | | V | | V | | |Seek | | | |V | V | | V | | V | | |Read/DMA (2) | V | V | V |V | V | | V | V | V | V | |Read Long | V | | V |V | V | | V | | V | V | |Write/DMA | V | | V |V | V | V | V | | V | | |Write Long | V | | V |V | V | V | V | | V | | |Format Track | | | |V | V | V | V | | V | V | |Read Verify (2) | V | V | V |V | | V | | V | | | |Execute Diagnostics | | | | | | | | | V | | |Set Drive | | | | | | | | | | | |Parameters | | | | | | | | | | | |Read Multiple (2) | V | V | V |V | V | V | | V | V | V | |Write Multiple | V | | V |V | V | V | V | | V | V | |Set Multiple | | | |V | | | | | V | | |Read Buffer | | | | | | | | | | V | |Write Buffer | | | | | | | | | | V | |Identify Drive | | | | | | | | | | | |Set Features | | | |V | V | | V | | V | V | |Mode Sense/Mode Select| | | |V | | | | | | V | |Invalid Command | | | |V | | | | | V | | +----------------------+---+---+----+--+----+---+---+----+---+----+ BBD - Bad Block Detected DWF - Drive Write Fault UNC - Uncorrectable Data Error DSC - Drive Seek Complete Erorr IDNF - ID Not Found CORR - Data was Corrected AC - Abort Comman Error ERR - Error Bit in Status Register DRDY - Drive not Ready Error V - Valid Error for Command HOST FIFO - Set when IORDY Timing violation Occurs (1) Also sets TK0 in Error Register if no track zero is found (2) Also sets DAMNF in Error Register if data address mark not found ********************************************************************** G E N E R A L ********************************************************************** WESTERN ENHANCED EIDE Enhanced IDE Backgrounder ========================= The Computer Market and the IDE Interface: ------------------------------------------ The computer marketplace is segmented into various classes of machines divided by user expectations in terms of cost, performance, compatibility and ease-of-use. The largest distinct segment today is the personal computer market, characterized by single- user products supporting a broad user base. The usage of these machines in business and home environments has dictated an emphasis on cost and compatibility. Historically, cost and compatibility in the personal computer marketplace have been more important to mainstream users than very high performance. The PC user has simply not been willing to bear the added cost or potential lack of compatibility that highest performance solutions imply. Given this criteria, the mainstream volume personal computer market has standardized on the IDE interface for its primary storage needs. The success of the IDE interface in the PC market has resulted primarily from a perfect match between IDE's offerings and the requirements of the market it serves. Specifically, its low cost of connection, compatibility, and ease-of-use, compared to alternative interfaces such as the Small Computer System Interface (SCSI), have been essential attributes in satisfying an expansive price-sensitive user group. In addition, because of the broad user base it serves, the personal computer market has traditionally required only hard disk support to meet its mass storage requirements. IDE has therefore evolved as a drive-only interface. Increasing Need for Performance and Connectivity Flexibility: ------------------------------------------------------------- As the personal computer market matures, it continues to display an increased emphasis on enhanced performance and connectivity capabilities, while maintaining its focus on cost, compatibility and ease-of-use. The market criteria has therefore grown to include higher performance attributes without sacrificing the needs of its price sensitive customers. It is in the realm of higher performance characteristics and connectivity that today's traditional IDE interface faces challenges. Other existing interfaces, such as SCSI, provide greater flexibility and performance options to meet these requirements, while failing to provide IDE's benefits of compatibility, cost and ease-of-use. Western Digital's Enhanced IDE technology addresses the performance and connectivity challenges facing the IDE interface. Enhanced IDE is designed to extend the attributes of the IDE interface so that its characteristics more effectively match the new requirements of the evolving personal computer market, without forfeiting its traditional benefits. Western Digital and the IDE Interface - Building upon Expertise: ---------------------------------------------------------------- Western Digital's Enhanced IDE technology evolves from the company's storage expertise within the personal computer marketplace. In 1984, Western Digital developed the WD1002 floppy and ST506 interface hard disk controller that IBM utilized in their PC/AT systems. The success of the PC/AT architecture led to the massive growth of the IBM PC/AT compatible market. This dramatic growth was in part fueled by WD1002 compatible hard disk controllers and later by Western Digital's standard-setting WD1003 series of AT controllers. As the market expanded and became more price sensitive, Western Digital defined the need for integration of the AT controller electronics within the disk drive. By working with Compaq Computer Corporation, Western Digital again drove the technology by proposing the IDE (Integrated Drive Electronics) interface which was implemented in the industry's first IDE drive in 1986. The disk drives used in personal computers have standardized around IDE since this introduction. ATAPI Specification: -------------------- Now, Western Digital continues to lead the industry with its IDE interface expertise via Enhanced IDE, an approach that expands upon the existing attributes of the IDE interface and extends its usage into more demanding environments. Enhanced IDE not only incorporates high speed host transfer capabilities, support of high capacity disk drives, and multiple device connectivity, but it also includes non-disk peripheral support via the Western Digital authored ATAPI (AT Attachment Packet Interface) specification. This enhanced IDE-ATA specification enables connectivity of non-disk peripherals such as CD-ROM and tape drives. The Western Digital defined ATAPI specification, with participation and endorsement by key market-making OEMS, CD-ROM suppliers and operating system suppliers, is yet another example of Western Digital's commitment to the evolution of the IDE interface. Enhanced IDE: ------------- Enhanced IDE removes many of the existing limitations and issues associated with the current IDE interface. Removal of these limitations enables IDE to grow with the industry's increased mass storage requirements without sacrificing its key cost, compatibility and ease-of- use attributes. The historical limitations of IDE relative to other interfaces, such as SCSI, have not threatened IDE's dominance of the PC marketplace to date. Upcoming personal computer systems, architected around high performance processors, more complex operating systems, and more demanding software applications, have developed storage requirements beyond the realm of today's IDE capabilities, challenging IDE's dominant role in the PC market. Specifically, the IDE interface is less flexible and limited in key areas of performance and connectivity relative to the SCSI interface: The IDE interface supports two disk drives. The SCSI interface supports multiple devices includingprinters, CD-ROM, tape drives as well as hard disk drives. The IDE interface is limited to 528MB hard disk capacity as a result of the Int 13h BIOS interface used to access IDE drives. The SCSI interface is not limited in capacity. The IDE interface typically offers 2-3MB/sec host transfer rates on standard ISA bus architected machines. The SCSI interface offers 10MB/sec FAST transfers and up to 20MB/sec FAST/WIDE host throughput. Western Digital's Enhanced IDE technology offers solutions to the existing constraints associated with the current IDE interface such as capacity limitations, slower host transfers, and connectivity issues associated with the IDE interface and thereby enables a cost effective, compatible, and easy-to-use interface solution for the next generation of personal computers. Components of Enhanced IDE: --------------------------- Enhanced IDE focuses on removing four primary limitations of the existing IDE interface. These include: Removal of the 528MB capacity barrier Breaking the IDE transfer bottleneck Supporting multiple IDE devices Enabling non-disk peripheral connectivity, such as CD-ROM Below, each of these limitations is discussed and resolved in detail. Removal of Capacity Limitations ------------------------------- A barrier in implementing IDE disk drives greater than 528MB exists in today's standard AT system BIOS. This barrier is based on historical reasons dating from the development of the original AT machine in 1984. Specifically, it is a limitation of the combined Interrupt 13 software interface and the IDE interface. The goal is to change the system BIOS such that this barrier no longer exists, thereby enabling the usage of high capacity IDE disk drives. Western Digitial's specification for removing the 528MB barrier is a simple yet effective method for implementation by BIOS suppliers and system manufactures who write their own BIOS. The capacity limitation exists due to the number of bits allocated for specifying the cylinder, head, and sector address information at both the Int 13h interface level and at the IDE interface level. Because Int 13h and IDE specify differing values, combining these two interfaces produces an artificial 528MB barrier as shown below: BIOS IDE --------------------------------------------------------------- Limitation Max Sectors/Track 63 225 63 Number of Heads 255 16 16 Number of Cylinders 1024 65536 1024 Maximum Capacity 8.4GB 136.9GB 528MB Two solutions exist that resolve the existing 528MB barrier problem. The first method is to have the BIOS translate the CHS address at the 13h interface to the CHS parameters being used at the drive interface. The Enhanced IDE proposal to break the 528MB barrier is to utilize the second method of modifying the Int 13h BIOS so that it translates the cylinder, head, sector information passed to it via Int 13 into a 28 bit Logical Block Address (LBA). The LBA solution is believed to be the best method of breaking the 528MB barrier because it provides a clean and efficient way for future operating system drivers to access IDE drives. The LBA translation is loaded into the drive's task file registers. Bit 6 of the drive's SDH register is set to indicate to the drive's firmware that it should interpret the information in its task file registers as LBA rather than cylinder, head and sector information. This scheme will allow for the full use of all of the bits allocated for CHS information at the Int 13h interface, thereby supporting up to 8.4GB. Using a logical block addressing scheme is attractive primarily because it is 100 percent compatible with BIOS Int 13 and allows for reduced overhead, producing higher performance. The logical block addressing scheme provides the compatibility essential for personal computer usage as well as enables the implementation of higher capacity disk drives required for high performance machines. Western Digital's LBA scheme has been successfully demonstrated by key system manufacturers writing their own BIOS and by those working in conjunction with their BIOS suppliers. Systems shipping in calendar Q4, 1993 will implement this scheme with the Western Digital Caviar AC2540. Bypassing the AT-IDE Host Transfer Bottleneck: ---------------------------------------------- The ISA bus capabilities are designed to sustain host throughput data rates of roughly 2-3MB/sec. Relative to SCSI host transfer rates of 5MB, 10MB, and 20MB/sec, the ISA bus is painfully slow for higher performance applications. Because AT personal computers did not necessarily demand the higher performance obtained by their workstation or file server counterparts, 2-3MB/sec wasn't considered a limiting factor. In addition, the ISA bus capabilities of 2-3MB/sec did not present a throughput problem because data rates coming off the media were roughly only 5Mbits/sec, and not a challenge to the host throughput. As disk drive areal density technologies progressed, media data rates began to exceed the 2-3MB/sec ISA host throughput. Buffering either on the system or the drive was necessary to maintain performance. The industry's most recent drive offerings far exceed the ISA bus host throughput by providing media data rates of up to 48Mbit/sec. Due to these factors, increased buffering is not a cost effective alternative to faster host throughput. Fast PIO Transfers: ------------------- Other peripherals within the computer, such as video, resolved their throughput problems via local bus architectures providing a potential path for improved performance. IDE local bus solutions, leveraged from the success of video local bus, began appearing in 1992, as a way to enhance data throughput. These solutions mapped the IDE data port to the local bus, bypassing the ISA bus and enabling the maximization of throughput from the media to the drive buffer, on to the host. These solutions were still not competitive with Fast SCSI (10MB/sec) due to the "blind" transfer nature of the PIO transfers. "Blind PIO" transfers indicate host control of data throughput with the host requesting data (master) and the drive responding (slave). With blind PIO transfers, the host is unaware or "blind" when buffered drive bandwidth is 100% available for host transfers. Because there are cases when only a percentage of bandwidth is available, blind PIO host requests for data from the drive are based on the worst case bandwidth availability. This means that even when the ISA bottleneck is bypassed by connection directly to the local bus, inability to utilize 100% drive bandwidth prevents full optimization of host throughput. Enhanced IDE incorporates an operation called "Flow Control Using IORDY" (I/O Channel Ready) which allows the drive to "throttle" the host when necessary and enable burst transfers to take advantage of 100% of the bandwidth. Flow Control thereby gives control of the data transfer to the drive and eliminates the inefficiencies of blind PIO by setting the host to maximum drive bandwidth support. This means that when 100% drive bandwidth is available, the drive will take control and transfer data to the host. This operation, based on approved Mode 3 PIO timings of 180ns cycle times from the Small Form Factor Committee, supports transfer rates up to 11MB/sec competitive with FAST SCSI solutions. Flow Control is enabled on the drive by the host issuing a Set Features command, so that both the host and drive side support this operation. Western Digital's 540MB drives (shipping beginning September, 1993) support flow control using IORDY and will be implemented into machines that take advantage of this feature via low cost ASICS whose functionality will later be incorporated into core logic chipset solutions. DMA Transfers -------------- Although PIO is the standard transfer method supported by the industry and presents no incompatibility issues (see footnote), another transfer option exists that provides incremental transfer benefits beyond PIO. Direct Memory Access (DMA) is based on data transfer directly to memory rather than via the CPU. DMA transfers are "throttled" and therefore have historically offered the benefit of maximizing data throughput. The throttling mechanism associated with DMA has historically enabled improved data transfers relative to standard PIO. Type B DMA was defined with the arrival of Extended Industry Standard Architecture (EISA), and is specified at 4.0MB/sec transfer rates offering an advantage to the standard 2-3MB/sec PIO data rates. Although this is an improvement to the standard ISA bus timings, Type B DMA remains uncompetitive with FAST SCSI timings of 10MB/sec. With the advent of local bus solutions, a new DMA transfer has emerged in conjuction with PCI. Type F DMA is defined to support 8.33MB/sec and 6.67MB/sec data rates, a large improvement over Type B DMA. In conjunction with chipsets capable of supporting 6.67MB and 8.33MB/sec data rates, the Small Form Factor Committee has approved a new multiword DMA Mode 1 timing specification of a 150ns cycle time. This enables DMA transfers up to 13MB/sec for future data rate improvement by allowing multiple words to be transferred for any given request command. PCI chip sets will be shipping with both EISA (Type B) and ISA (Type F) configurations in the calendar CYQ4'1993 time frame. PIO versus DMA: --------------- The disadvantage of DMA transfer operations is that the PC/AT hard disk controller and later IDE, evolved around PIO data transfers. Therefore, the system Int 13h BIOS and the embedded operating system device drivers have supported PIO transfers versus DMA transfers. This simply means that BIOS changes and external device drivers are necessary to achieve the incremental performance that DMA offers. Western Digital's Enhanced IDE program supports system manufacturers' choice of either PIO transfers via Flow control with IORDY for Mode 3 PIO data rates or DMA transfers (both Type B and Type F) via the development of external DMA device drivers supporting Western Digital hard disk drives. Product platforms based on both high speed transfer options will be in production in calendar fourth quarter 1993. Supporting Multiple IDE Devices: -------------------------------- The original IBM PC/AT defined support for two hard disk controllers and allowed support for up to four disk drives via a primary and secondary controller. The original BIOS and operating system drivers, however, only supported the primary controller, limiting the standard PC configuration to two disk drives. Today's operating systems now offer both primary and secondary controller support providing an opportunity to extend peripheral attachment capabilities with IDE. The addition of a second connector via a hardware change is a simple, low cost solution that allows for multiple IDE peripheral connectivity. The cost of a second IDE connector is less than $1.00. Most core logic and Super I/O devices have already integrated the capability to support either the primary or secondary address decode logic and therefore the cost of the secondary port is simply the 40 pin connector and surrounding transceivers and resistors. For $1.00, dual IDE connectors offer support for four IDE devices and satisfy the expansion needs of the majority of the mainstream personal computer market, a very cost effective alternative to connectivity via SCSI. Western Digital's Enhanced IDE program works with system manufacturers to understand the BIOS implications of a secondary channel for support of two additional IDE devices. The BIOS must be able to determine the physical location of the drive based on the Int 13h drive number . Since DOS 3.0 and later will support up to seven disk drives, only the system BIOS Interrupt 13h needs to be modified to support primary and secondary IDE. Windows 3.1 accesses the disk via Interrupt 13h calls to the BIOS. Again, all that is required is modification to the system BIOS to support dual channel IDE. IBM OS/2 2.0 and 2.1 as well as MS/IBM OS/2 1.31 all support four IDE drives on dual IDE connectors via their drivers. Netware is hardcoded to support four IDE connectors or 8 IDE devices. Dual channel IDE support will be in the final release of Windows NT. Dual channel IDE not only enables the cost effective and easy implementation to support multiple disk drives, it presents the opportunity to expand IDE into non-disk peripheral support. A slow speed channel and a high speed channel can be developed for efficient implementation of storage solutions via high performance hard disk drives and mass data storage vehicles such as CD-ROM and tape drives. Enabling Non-disk Peripheral Connectivity: ------------------------------------------ The upcoming high performance desktop machines are demanding additional storage peripheral support beyond hard disk drives. Specifically, CD-ROM and tape drives will demonstrate rapid unit growth rates as these peripherals become a more standard part of the desktop's configuration. Today's CD- ROMs and tape drives have multiple interfaces that present compatibility and performance issues. Development of a standard IDE interface for both CD-ROMs and tape drives solves cost, compatibility, performance, and ease-of-use issues in conjunction with enabling the attachment of non-disk devices via the IDE interface. Western Digital, with its AT interface expertise, has taken the leadership position in expanding the IDE interface to support non-disk peripherals by authoring the AT Attachment Packet Interface (ATAPI). The specification defines a standard method for interfacing to a CD-ROM drive (and other non-disk devices) utilizing the existing ATA host computer hardware and cabling. ATAPI supplements the definitions of an ATA mass storage peripheral found in the ATA specification and is compatible with existing ATA hardware without any changes or additional pins. Traditional computer architecture has used a register based transport mechanism. Modern architectures now use packet-based transport mechanisms. ATAPI is an enhancement to IDE that follows this trend. Benefits of including a packet-based scheme means adding very few IDE operation codes. The ATAPI specification adds only a single new IDE command to obtain functionality and only two additional new IDE commands to address compatibility. Once a packet-based interface was defined, the next issue was deciding what command packets definitions to utilize. Given widespread support for SCSI within peripherals and within existing operating systems, it was decided to derive ATAPI command packets from SCSI to minimize development time and expense. The ATAPI specification is being reviewed by an industry working group that consists of market-making system manufacturers, CD-ROM suppliers, silicon designers, BIOS developers, and Western Digital. The objective is to finalize the ATAPI specification around which these companies will design and manufacture products for the personal computer industry. Although the exact strategy has yet to be decided upon, the document will eventually be submitted to a standards committee for adoption. Putting it All Together ------------------------ Support for four IDE devices Fast IDE port for disk drives Slow IDE port for CD-ROMs and tape True plug and play Lowest cost of connection Overlapped I/Os for higher performance The Big Picture: ---------------- It is clear that the mass storage needs of the personal computer industry are expanding to include higher performance and connectivity requirements. Enhanced IDE was developed in response to these requirements. The industry is already embracing Enhanced IDE and its elements of improved functionality, performance, and connectivity by introducing products in the calendar fourth quarter of 1993. These products include BIOS support for >528MB IDE hard disk drives, the shipment of >528MB IDE drives themselves, silicon and controller products supporting fast PIO and DMA transfers, and hardware supporting dual channel IDE for multiple device connectivity. Momentum in the development of the industry's first standard IDE non- disk peripherals is well underway with the industry's first IDE CD-ROMs anticipated to ship in calendar first quarter 1994. SCSI and IDE Scorecard: The industry activity backed by real Enhanced IDE products means that IDE has met the challenge in addressing the industry's new requirements. IDE's cost effectiveness and compatibility advantages, matched now with high performance and connectivity attributes make it a solid storage interface solution well into the future. A new comparison of the AT/SCSI scorecard reveals the successful approach of Enhanced IDE: Standard AT Interface -------------------- * The IDE interface supports two disk drives. * IDE is a hard disk only interface. * The IDE interface is limited to 528MB hard disk capacity as as result of the Int 13h BIOS interface used to access IDE drives. * The IDE interface is typically limited to 2-3MB/sec host throughput. With Enhanced IDE ----------------- * The IDE interface supports four IDE devices with dual channel IDE and more with multiple IDE connectors. * The IDE interface supports non-disk peripherals such as IDE CD-ROM, IDE Tape. * With LBA, the IDE interface supports up to 8.4G of hard disk capacity. * With Mode 3 PIO and multiword DMA mode 1, data transfer rates with IDE drives can be from 11MB/sec up to 13MB/sec. With Enhanced IDE, the IDE interface has become a mass storage interface for personal computers and is no longer simply a disk drive interface. Enhanced IDE complements SCSI in that it remains primarily an internal interface solution with SCSI as an external interface solution. Western Digital is a registered trademark of Western Digital Corporation. All marks mentioned herein belong to other companies. PIO transfers are based on using the CPU to perform the data transfer (Processor I/O) and is the standard transfer method supported within all existing BIOS and all embedded operating system device drivers. PIO implies compatibility with existing BIOS/OS and therefore does not require added device driver support for operation.